Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 4/15 and 16-symbol mapping, and bit interleaving method using same

ABSTRACT

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application Nos.10-2014-0061873 and 10-2015-0009139, filed May 22, 2014 and Jan. 20,2015, which are hereby incorporated by reference herein in theirentirety.

BACKGROUND

1. Technical Field

The present disclosure relates generally to an interleaver and, moreparticularly, to a bit interleaver that is capable of distributing bursterrors occurring in a digital broadcast channel.

2. Description of the Related Art

Bit-Interleaved Coded Modulation (BICM) is bandwidth-efficienttransmission technology, and is implemented in such a manner that anerror-correction coder, a bit-by-bit interleaver and a high-ordermodulator are combined with one another.

BICM can provide excellent performance using a simple structure becauseit uses a low-density parity check (LDPC) coder or a Turbo coder as theerror-correction coder. Furthermore, BICM can provide high-levelflexibility because it can select modulation order and the length andcode rate of an error correction code in various forms. Due to theseadvantages, BICM has been used in broadcasting standards, such as DVB-T2and DVB-NGH, and has a strong possibility of being used in othernext-generation broadcasting systems.

However, in spite of those advantages, BICM suffers from the rapiddegradation of performance unless burst errors occurring in a channelare appropriately distributed via the bit-by-bit interleaver.Accordingly, the bit-by-bit interleaver used in BICM should be designedto be optimized for the modulation order or the length and code rate ofthe error correction code.

SUMMARY

At least one embodiment of the present invention is directed to theprovision of an intra-BICM bit interleaver that can effectivelydistribute burst errors occurring in a broadcasting system channel.

At least one embodiment of the present invention is directed to theprovision of a bit interleaver that is optimized for an LDPC coderhaving a length of 16200 and a code rate of 4/15 and a modulatorperforming 16-symbol mapping and, thus, can be applied tonext-generation broadcasting systems, such as ATSC 3.0.

In accordance with an aspect of the present invention, there is provideda bit interleaver, including a first memory configured to store alow-density parity check (LDPC) codeword having a length of 16200 and acode rate of 4/15; a processor configured to generate an interleavedcodeword by interleaving the LDPC codeword on a bit group basis, thesize of the bit group corresponding to a parallel factor of the LDPCcodeword; and a second memory configured to provide the interleavedcodeword to a modulator for 16-symbol mapping.

The 16-symbol mapping may be NUC (Non-Uniform Constellation) symbolmapping corresponding to 16 constellations (symbols).

The parallel factor may be 360, and each of the bit groups may include360 bits.

The LDPC codeword may be represented by (u₀, u₁, . . . , u_(N) _(ldpc)⁻¹) (where N_(ldpc) is 16200), and may be divided into 45 bit groupseach including 360 bits, as in the following equation:X _(j) ={u _(k)|360×j≦k<360×(j+1), 0≦k<N _(ldpc)} for 0≦j<N _(group)where X_(j) is an j-th bit group, N_(ldpc) is 16200, and N_(group) is45.

The interleaving may be performed using the following equation usingpermutation order:Y _(j) =X _(π(j)) 0≦j≦N _(group)where X_(j) is the j-th bit group, Y_(j) is an interleaved j-th bitgroup, and π(j) is a permutation order for bit group-based interleaving(bit group-unit interleaving).

The permutation order may correspond to an interleaving sequencerepresented by the following equation:interleaving sequence={34 3 19 35 25 2 17 36 26 38 0 40 27 10 7 43 21 2815 6 1 37 18 30 32 33 29 22 12 13 5 23 44 14 4 31 20 39 42 11 9 16 41 824}

In accordance with another aspect of the present invention, there isprovided a bit interleaving method, including storing an LDPC codewordhaving a length of 16200 and a code rate of 4/15; generating aninterleaved codeword by interleaving the LDPC codeword on a bit groupbasis corresponding to the parallel factor of the LDPC codeword; andoutputting the interleaved codeword to a modulator for 16-symbolmapping.

In accordance with still another aspect of the present invention, thereis provided a BICM device, including an error-correction coderconfigured to output an LDPC codeword having a length of 16200 and acode rate of 4/15; a bit interleaver configured to interleave the LDPCcodeword on a bit group basis corresponding to the parallel factor ofthe LDPC codeword and output the interleaved codeword; and a modulatorconfigured to perform 16-symbol mapping on the interleaved codeword.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will be more clearly understood from the following detaileddescription taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a block diagram illustrating a broadcast signal transmissionand reception system according to an embodiment of the presentinvention;

FIG. 2 is an operation flowchart illustrating a broadcast signaltransmission and reception method according to an embodiment of thepresent invention;

FIG. 3 is a diagram illustrating the structure of a parity check matrix(PCM) corresponding to an LDPC code to according to an embodiment of thepresent invention;

FIG. 4 is a diagram illustrating the bit groups of an LDPC codewordhaving a length of 64800;

FIG. 5 is a diagram illustrating the bit groups of an LDPC codewordhaving a length of 16200;

FIG. 6 is a diagram illustrating interleaving that is performed on a bitgroup basis in accordance with an interleaving sequence;

FIG. 7 is a block diagram illustrating a bit interleaver according to anembodiment of the present invention; and

FIG. 8 is an operation flowchart illustrating a bit interleaving methodaccording to an embodiment of the present invention.

DETAILED DESCRIPTION

Embodiments of the present invention will be described in detail belowwith reference to the accompanying drawings. Repeated descriptions anddescriptions of well-known functions and configurations that have beendeemed to make the gist of the present invention unnecessarily obscurewill be omitted below. The embodiments of the present invention areintended to fully describe the present invention to persons havingordinary knowledge in the art to which the present invention pertains.Accordingly, the shapes, sizes, etc. of components in the drawings maybe exaggerated to make the description obvious.

Embodiments of the present invention will be described in detail belowwith reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a broadcast signal transmissionand reception system according to an embodiment of the presentinvention.

Referring to FIG. 1, it can be seen that a BICM device 10 and a BICMreception device 30 communicate with each other over a wireless channel20.

The BICM device 10 generates an n-bit codeword by encoding k informationbits 11 using an error-correction coder 13. In this case, theerror-correction coder 13 may be an LDPC coder or a Turbo coder.

The codeword is interleaved by a bit interleaver 14, and thus theinterleaved codeword is generated.

In this case, the interleaving may be performed on a bit group basis (bya unit of a bit group). In this case, the error-correction coder 13 maybe an LDPC coder having a length of 16200 and a code rate of 4/15. Acodeword having a length of 16200 may be divided into a total of 45 bitgroups. Each of the bit groups may include 360 bits, i.e., the parallelfactor of an LDPC codeword.

In this case, the interleaving may be performed on a bit group basis (bya unit of a bit group) in accordance with an interleaving sequence,which will be described later.

In this case, the bit interleaver 14 prevents the performance of errorcorrection code from being degraded by effectively distributing bursterrors occurring in a channel. In this case, the bit interleaver 14 maybe separately designed in accordance with the length and code rate ofthe error correction code and the modulation order.

The interleaved codeword is modulated by a modulator 15, and is thentransmitted via an antenna 17.

In this case, the modulator 15 may be based on a concept includingsymbol mapper (symbol mapping device). In this case, the modulator 15may be a symbol mapping device performing 16-symbol mapping which mapscodes onto 16 constellations (symbols).

In this case, the modulator 15 may be a uniform modulator, such as aquadrature amplitude modulation (QAM) modulator, or a non-uniformmodulator.

The modulator 15 may be a symbol mapping device performing NUC(Non-Uniform Constellation) symbol mapping which uses 16 constellations(symbols).

The signal transmitted via the wireless channel 20 is received via theantenna 31 of the BICM reception device 30, and, in the BICM receptiondevice 30, is subjected to a process reverse to the process in the BICMdevice 10. That is, the received data is demodulated by a demodulator33, is deinterleaved by a bit deinterleaver 34, and is then decoded byan error correction decoder 35, thereby finally restoring theinformation bits.

It will be apparent to those skilled in the art that the above-describedtransmission and reception processes have been described within aminimum range required for a description of the features of the presentinvention and various processes required for data transmission may beadded.

FIG. 2 is an operation flowchart illustrating a broadcast signaltransmission and reception method according to an embodiment of thepresent invention.

Referring to FIG. 2, in the broadcast signal transmission and receptionmethod according to this embodiment of the present invention, input bits(information bits) are subjected to error-correction coding at stepS210.

That is, at step S210, an n-bit codeword is generated by encoding kinformation bits using the error-correction coder.

In this case, step S210 may be performed as in an LDPC encoding method,which will be described later.

Furthermore, in the broadcast signal transmission and reception method,an interleaved codeword is generated by interleaving the n-bit codewordon a bit group basis at step S220.

In this case, the n-bit codeword may be an LDPC codeword having a lengthof 16200 and a code rate of 4/15. The codeword having a length of 16200may be divided into a total of 45 bit groups. Each of the bit groups mayinclude 360 bits corresponding to the parallel factors of an LDPCcodeword.

In this case, the interleaving may be performed on a bit group basis (bya unit of a bit group) in accordance with an interleaving sequence,which will be described later.

Furthermore, in the broadcast signal transmission and reception method,the encoded data is modulated at step S230.

That is, at step S230, the interleaved codeword is modulated using themodulator.

In this case, the modulator may be based on a concept including symbolmapper (symbol mapping device). In this case, the modulator may be asymbol mapping device performing 16-symbol mapping which maps codes onto16 constellations (symbols).

In this case, the modulator may be a uniform modulator, such as a QAMmodulator, or a non-uniform modulator.

The modulator may be a symbol mapping device performing NUC (Non-UniformConstellation) symbol mapping which uses 16 constellations (symbols).

Furthermore, in the broadcast signal transmission and reception method,the modulated data is transmitted at step S240.

That is, at step S240, the modulated codeword is transmitted over thewireless channel via the antenna.

Furthermore, in the broadcast signal transmission and reception method,the received data is demodulated at step S250.

That is, at step S250, the signal transmitted over the wireless channelis received via the antenna of the receiver, and the received data isdemodulated using the demodulator.

Furthermore, in the broadcast signal transmission and reception method,the demodulated data is deinterleaved at step S260. In this case, thedeinterleaving of step S260 may be reverse to the operation of stepS220.

Furthermore, in the broadcast signal transmission and reception method,the deinterleaved codeword is subjected to error correction decoding atstep S270.

That is, at step S270, the information bits are finally restored byperforming error correction decoding using the error correction decoderof the receiver.

In this case, step S270 corresponds to a process reverse to that of anLDPC encoding method, which will be described later.

An LDPC code is known as a code very close to the Shannon limit for anadditive white Gaussian noise (AWGN) channel, and has the advantages ofasymptotically excellent performance and parallelizable decodingcompared to a turbo code.

Generally, an LDPC code is defined by a low-density parity check matrix(PCM) that is randomly generated. However, a randomly generated LDPCcode requires a large amount of memory to store a PCM, and requires alot of time to access memory. In order to overcome these problems, aquasi-cyclic LDPC (QC-LDPC) code has been proposed. A QC-LDPC code thatis composed of a zero matrix or a circulant permutation matrix (CPM) isdefined by a PCM that is expressed by the following Equation 1:

$\begin{matrix}{{H = \begin{bmatrix}J^{a_{11}} & J^{a_{12}} & \ldots & J^{a_{1n}} \\J^{a_{21}} & J^{a_{22}} & \ldots & J^{a_{2n}} \\\vdots & \vdots & \ddots & \vdots \\J^{a_{m\; 1}} & J^{a_{m\; 2}} & \ldots & J^{a_{mn}}\end{bmatrix}},{{{for}\mspace{14mu} a_{ij}} \in \left\{ {0,1,\ldots\mspace{14mu},{L - 1},\infty} \right\}}} & (1)\end{matrix}$

In this equation, J is a CPM having a size of L×L, and is given as thefollowing Equation 2. In the following description, L may be 360.

$\begin{matrix}{J_{L \times L} = \begin{bmatrix}0 & 1 & 0 & \ldots & 0 \\0 & 0 & 1 & \ldots & 0 \\\vdots & \vdots & \vdots & \ddots & \vdots \\0 & 0 & 0 & \ldots & 1 \\1 & 0 & 0 & \ldots & 0\end{bmatrix}} & (2)\end{matrix}$

Furthermore, J^(i) is obtained by shifting an L×L identity matrix I(J⁰)to the right i (0≦i<L) times, and j^(∞) is an L×L zero matrix.Accordingly, in the case of a QC-LDPC code, it is sufficient if onlyindex exponent i is stored in order to store J^(i), and thus the amountof memory required to store a PCM is considerably reduced.

FIG. 3 is a diagram illustrating the structure of a PCM corresponding toan LDPC code to according to an embodiment of the present invention.

Referring to FIG. 3, the sizes of matrices A and C are g×K and(N−K−g)×(K+g), respectively, and are composed of an L×L zero matrix anda CPM, respectively. Furthermore, matrix Z is a zero matrix having asize of g×(N−K−g), matrix D is an identity matrix having a size of(N−K−g)×(N−K−g), and matrix B is a dual diagonal matrix having a size ofg×g. In this case, the matrix B may be a matrix in which all elementsexcept elements along a diagonal line and neighboring elements below thediagonal line are 0, and may be defined as the following Equation 3:

$\begin{matrix}{B_{g \times g} = \begin{bmatrix}I_{L \times L} & 0 & 0 & \ldots & 0 & 0 & 0 \\I_{L \times L} & I_{L \times L} & 0 & \ldots & 0 & 0 & 0 \\0 & I_{L \times L} & I_{L \times L} & \vdots & 0 & 0 & 0 \\\vdots & \vdots & \vdots & \ddots & \vdots & \vdots & \vdots \\0 & 0 & 0 & \ldots & I_{L \times L} & I_{L \times L} & 0 \\0 & 0 & 0 & \ldots & 0 & I_{L \times L} & I_{L \times L}\end{bmatrix}} & (3)\end{matrix}$where I_(L×L) is an identity matrix having a size of L×L.

That is, the matrix B may be a bit-wise dual diagonal matrix, or may bea block-wise dual diagonal matrix having identity matrices as itsblocks, as indicated by Equation 3. The bit-wise dual diagonal matrix isdisclosed in detail in Korean Patent Application Publication No.2007-0058438, etc.

In particular, it will be apparent to those skilled in the art that whenthe matrix B is a bit-wise dual diagonal matrix, it is possible toperform conversion into a Quasi-cyclic form by applying row or columnpermutation to a PCM including the matrix B and having a structureillustrated in FIG. 3.

In this case, N is the length of a codeword, and K is the length ofinformation.

The present invention proposes a newly designed QC-LDPC code in whichthe code rate thereof is 4/15 and the length of a codeword is 16200, asillustrated in the following Table 1. That is, the present inventionproposes an LDPC code that is designed to receive information having alength of 4320 and generate an LDPC codeword having a length of 16200.

Table 1 illustrates the sizes of the matrices A, B, C, D and Z of theQC-LDPC code according to the present invention:

TABLE 1 Code Sizes rate Length A B C D Z 4/15 16200 1080 × 1080 × 10800× 10800 × 1080 × 4320 1080 5400 10800 10800

The newly designed LDPC code may be represented in the form of asequence (progression), an equivalent relationship is establishedbetween the sequence and matrix (parity bit check matrix), and thesequence may be represented, as follows:

Sequence Table

1st row: 19 585 710 3241 3276 3648 6345 9224 9890 10841

2nd row: 181 494 894 2562 3201 4382 5130 5308 6493 10135

3rd row: 150 569 919 1427 2347 4475 7857 8904 9903

4th row: 1005 1018 1025 2933 3280 3946 4049 4166 5209

5th row: 420 554 778 6908 7959 8344 8462 10912 11099

6th row: 231 506 859 4478 4957 7664 7731 7908 8980

7th row: 179 537 979 3717 5092 6315 6883 9353 9935

8th row: 147 205 830 3609 3720 4667 7441 10196 11809

9th row: 60 1021 1061 1554 4918 5690 6184 7986 11296

10th row: 145 719 768 2290 2919 7272 8561 9145 10233

11st row: 388 590 852 1579 1698 1974 9747 10192 10255

12nd row: 231 343 485 1546 3155 4829 7710 10394 11336

13rd row: 4381 5398 5987 9123 10365 11018 11153

14th row: 2381 5196 6613 6844 7357 8732 11082

15th row: 1730 4599 5693 6318 7626 9231 10663

An LDPC code that is represented in the form of a sequence is beingwidely used in the DVB standard.

According to an embodiment of the present invention, an LDPC codepresented in the form of a sequence is encoded, as follows. It isassumed that there is an information block S=(s₀, s₁, . . . , s_(K−1))having an information size K. The LDPC encoder generates a codewordΛ=(λ₀, λ₁, λ₂, . . . , λ_(N−1)) having a size of N=K+M₁+M₂ using theinformation block S having a size K. In this case, M₁=g, and M₂=N−K−g.Furthermore, M₁ is the size of parity bits corresponding to the dualdiagonal matrix B, and M₂ is the size of parity bits corresponding tothe identity matrix D. The encoding process is performed, as follows:

Initialization:λ_(i) =s _(i) for i=0, 1, . . . , K−1p _(j)=0 for j=0, 1, . . . , M ₁ +M ₂−1  (4)

First information bit λ₀ is accumulated at parity bit addressesspecified in the 1st row of the sequence of the Sequence Table. Forexample, in an LDPC code having a length of 16200 and a code rate of4/15, an accumulation process is as follows:

p₁₉=p₁₉⊕λ₀ p₅₈₅=p₅₈₅⊕λ₀ p₇₁₀=p₇₁₀⊕λ₀ p₃₂₄₁=p₃₂₄₁⊕λ₀ p₃₂₇₆=p₃₂₇₆⊕λ₀p₃₆₄₈=p₃₆₄₈⊕λ₀ p₆₃₄₅=p₆₃₄₅⊕λ₀ p₉₂₂₄=p₉₂₂₄⊕λ₀ p₉₈₉₀=p₉₈₉₀⊕λ₀p₁₀₈₄₁=p₁₀₈₄₁⊕λ₀

where the addition ⊕ occurs in GF(2).

The subsequent L−1 information bits, that is, λ_(m), m=1, 2, . . . ,L−1, are accumulated at parity bit addresses that are calculated by thefollowing Equation 5:(x+m×Q ₁)mod M ₁ if x<M ₁M ₁+{(x−M ₁ +m×Q ₂)mod M ₂} if x≧M ₁  (5)where x denotes the addresses of parity bits corresponding to the firstinformation bit λ₀, that is, the addresses of the parity bits specifiedin the first row of the sequence of the Sequence Table, Q₁=M₁/L,Q₂=M₂/L, and L=360. Furthermore, Q₁ and Q₂ are defined in the followingTable 2. For example, for an LDPC code having a length of 16200 and acode rate of 4/15, M₁=1080, Q₁=3, M₂=10800, Q₂=30 and L=360, and thefollowing operations are performed on the second bit λ₁ using Equation5:p₂₂=p₂₂⊕λ₁ p₅₈₈=p₅₈₈⊕λ₁ p₇₁₃=p₇₁₃⊕λ₁ p₃₂₇₁=p₃₂₇₁⊕λ₁ p₃₃₀₆=p₃₃₀₆⊕λ₁p₃₆₇₈=p₃₆₇₈⊕λ₁ p₆₃₇₅=p₆₃₇₅⊕λ₁ p₉₂₅₄=p₉₂₅₄⊕λ₁ p₉₉₂₀=p₉₉₂₀⊕λ₁p₁₀₈₇₁=p₁₀₈₇₁⊕λ₁

Table 2 illustrates the sizes of M₁, Q₁, M₂ and Q₂ of the designedQC-LDPC code:

TABLE 2 Sizes Code rate Length M₁ M₂ Q₁ Q₂ 4/15 16200 1080 10800 3 30

The addresses of parity bit accumulators for new 360 information bitsfrom λ_(L) to λ_(2L−1) are calculated and accumulated from Equation 5using the second row of the sequence.

In a similar manner, for all groups composed of new L information bits,the addresses of parity bit accumulators are calculated and accumulatedfrom Equation 5 using new rows of the sequence.

After all the information bits from λ₀ to λ_(K−1) have been exhausted,the operations of the following Equation 6 are sequentially performedfrom i=1:p _(i) =p _(i) ⊕p _(i−1) for i=0, 1, . . . , M ₁−1  (6)

Thereafter, when a parity interleaving operation, such as that of thefollowing Equation 7, is performed, parity bits corresponding to thedual diagonal matrix B are generated:λ_(K+L·t+s) =p _(Q) ₁ _(·s+t) for 0≦s<L, 0≦t<Q ₁  (7)

When the parity bits corresponding to the dual diagonal matrix B havebeen generated using K information bits λ₀, λ₁, . . . , λ_(K−1), paritybits corresponding to the identity matrix D are generated using the M₁generated parity bits λ_(K), λ_(K+1), . . . , λ_(K+M) ₁ ⁻¹.

For all groups composed of L information bits from λ_(K) to λ_(K+M) ₁⁻¹, the addresses of parity bit accumulators are calculated using thenew rows (starting with a row immediately subsequent to the last rowused when the parity bits corresponding to the dual diagonal matrix Bhave been generated) of the sequence and Equation 5, and relatedoperations are performed.

When a parity interleaving operation, such as that of the followingEquation 8, is performed after all the information bits from λ_(K) toλ_(K+M) ₁ ⁻¹ have been exhausted, parity bits corresponding to theidentity matrix D are generated:λ_(K+M) ₁ _(+L·t+s) =p _(M) ₁ _(+Q) ₂ _(·s+t) for 0≦s<L, 0≦t<Q ₂  (8)

FIG. 4 is a diagram illustrating the bit groups of an LDPC codewordhaving a length of 64800.

Referring to FIG. 4, it can be seen that an LDPC codeword having alength of 64800 is divided into 180 bit groups (a 0th group to a 179thgroup).

In this case, 360 may be the parallel factor (PF) of the LDPC codeword.That is, since the PF is 360, the LDPC codeword having a length of 64800is divided into 180 bit groups, as illustrated in FIG. 4, and each ofthe bit groups includes 360 bits.

FIG. 5 is a diagram illustrating the bit groups of an LDPC codewordhaving a length of 16200.

Referring to FIG. 5, it can be seen that an LDPC codeword having alength of 16200 is divided into 45 bit groups (a 0th group to a 44thgroup).

In this case, 360 may be the parallel factor (PF) of the LDPC codeword.That is, since the PF is 360, the LDPC codeword having a length of 16200is divided into 45 bit groups, as illustrated in FIG. 5, and each of thebit groups includes 360 bits.

FIG. 6 is a diagram illustrating interleaving that is performed on a bitgroup basis in accordance with an interleaving sequence.

Referring to FIG. 6, it can be seen that interleaving is performed bychanging the order of bit groups by a designed interleaving sequence.

For example, it is assumed that an interleaving sequence for an LDPCcodeword having a length of 16200 is as follows:interleaving sequence={24 34 15 11 2 28 17 25 5 38 19 13 6 39 1 14 33 3729 12 42 31 30 32 36 40 26 35 44 4 16 8 20 43 21 7 0 18 23 3 10 41 9 2722}

Then, the order of the bit groups of the LDPC codeword illustrated inFIG. 4 is changed into that illustrated in FIG. 6 by the interleavingsequence.

That is, it can be seen that each of the LDPC codeword 610 and theinterleaved codeword 620 includes 45 bit groups, and it can be also seenthat, by the interleaving sequence, the 24th bit group of the LDPCcodeword 610 is changed into the 0th bit group of the interleaved LDPCcodeword 620, the 34th bit group of the LDPC codeword 610 is changedinto the 1st bit group of the interleaved LDPC codeword 620, the 15thbit group of the LDPC codeword 610 is changed into the 2nd bit group ofthe interleaved LDPC codeword 620, and the 11st bit group of the LDPCcodeword 610 is changed into the 3rd bit group of the interleaved LDPCcodeword 620, and the 2nd bit group of the LDPC codeword 610 is changedinto the 4th bit group of the interleaved LDPC codeword 620.

An LDPC codeword (u₀, u₁, . . . , u_(N) _(ldpc) ⁻¹) having a length ofN_(ldpc) (N_(ldpc)=16200) is divided into N_(group)=N_(ldpc)/360 bitgroups, as in Equation 9 below:X _(j) ={u _(k)|360×j≦k<360×(j+1), 0≦k<N _(ldpc)} for 0≦j<N_(group)  (9)where X_(j) is an j-th bit group, and each X_(j) is composed of 360bits.

The LDPC codeword divided into the bit groups is interleaved, as inEquation 10 below:Y _(j) =X _(π(j)) 0≦j≦N _(group)  (10)where Y_(j) is an interleaved j-th bit group, and π(j) is a permutationorder for bit group-based interleaving (bit group-unit interleaving).The permutation order corresponds to the interleaving sequence ofEquation 11 below:interleaving sequence={34 3 19 35 25 2 17 36 26 38 0 40 27 10 7 43 21 2815 6 1 37 18 30 32 33 29 22 12 13 5 23 44 14 4 31 20 39 42 11 9 16 41 824}  (11)

That is, when each of the codeword and the interleaved codeword includes45 bit groups ranging from a 0th bit group to a 44th bit group, theinterleaving sequence of Equation 11 means that the 34th bit group ofthe codeword becomes the 0th bit group of the interleaved codeword, the3th bit group of the codeword becomes the 1st bit group of theinterleaved codeword, the 19th bit group of the codeword becomes the 2ndbit group of the interleaved codeword, the 35th bit group of thecodeword becomes the 3rd bit group of the interleaved codeword, . . . ,the 8th bit group of the codeword becomes the 43th bit group of theinterleaved codeword, and the 24th bit group of the codeword becomes the44th bit group of the interleaved codeword.

In particular, the interleaving sequence of Equation 11 has beenoptimized for a case where 16-symbol mapping (NUC symbol mapping) isemployed and an LDPC coder having a length of 16200 and a code rate of4/15 is used.

FIG. 7 is a block diagram illustrating a bit interleaver according to anembodiment of the present invention.

Referring to FIG. 7, the bit interleaver according to the presentembodiment includes memories 710 and 730 and a processor 720.

The memory 710 stores an LDPC codeword having a length of 16200 and acode rate of 4/15.

The processor 720 generates an interleaved codeword by interleaving theLDPC codeword on a bit group basis corresponding to the parallel factorof the LDPC codeword.

In this case, the parallel factor may be 360. In this case, each of thebit groups may include 360 bits.

In this case, the LDPC codeword may be divided into 45 bit groups, as inEquation 9.

In this case, the interleaving may be performed using Equation 10 usingpermutation order.

In this case, the permutation order may correspond to the interleavingsequence represented by Equation 11.

The memory 730 provides the interleaved codeword to a modulator for16-symbol mapping.

In this case, the modulator may be a symbol mapping device performingNUC (Non-Uniform Constellation) symbol mapping.

The memories 710 and 730 may correspond to various types of hardware forstoring a set of bits, and may correspond to a data structure, such asan array, a list, a stack, a queue or the like.

In this case, the memories 710 and 730 may not be physically separatedevices, but may correspond to different addresses of a physicallysingle device. That is, the memories 710 and 730 are not physicallydistinguished from each other, but are merely logically distinguishedfrom each other.

The error-correction coder 13 illustrated in FIG. 1 may be implementedin the same structure as in FIG. 7.

That is, the error-correction coder may include memories and aprocessor. In this case, the first memory is a memory that stores anLDPC codeword having a length of 16200 and a code rate of 4/15, and asecond memory is a memory that is initialized to 0.

The memories may correspond to λ_(i) (i=0, 1, . . . , N−1) and P_(j)(j=0, 1, . . . , M₁+M₂−1), respectively.

The processor may generate an LDPC codeword corresponding to informationbits by performing accumulation with respect to the memory using asequence corresponding to a parity check matrix (PCM).

In this case, the accumulation may be performed at parity bit addressesthat are updated using the sequence of the above Sequence Table.

In this case, the LDPC codeword may include a systematic part λ₀, λ₁, .. . , λ_(K−1) corresponding to the information bits and having a lengthof 4320 (=K), a first parity part λ_(K+M) ₁ , λ_(K+M) ₁ ₊₁, . . . ,λ_(K+M) ₁ _(+M) ₂ ⁻¹ corresponding to a dual diagonal matrix included inthe PCM and having a length of 1080 (=M₁=g), and a second parity partλ_(K+M) ₁ , λ_(K+M) ₁ ₊₁, . . . , λ_(K+M) ₁ _(+M) ₂ ⁻¹ corresponding toan identity matrix included in the PCM and having a length of 10800(=M₂).

In this case, the sequence may have a number of rows equal to the sum(4320/360+1080/360=15) of a value obtained by dividing the length of thesystematic part, that is, 4320, by a CPM size L corresponding to thePCM, that is, 360, and a value obtained by dividing the length M₁ of thefirst parity part, that is, 1080, by 360.

As described above, the sequence may be represented by the aboveSequence Table.

In this case, the second memory may have a size corresponding to the sumM₁+M₂ of the length M₁ of the first parity part and the length M₂ of thesecond parity part.

In this case, the parity bit addresses may be updated based on theresults of comparing each x of the previous parity bit addresses,specified in respective rows of the sequence, with the length M₁ of thefirst parity part.

That is, the parity bit addresses may be updated using Equation 5. Inthis case, x may be the previous parity bit addresses, m may be aninformation bit index that is an integer larger than 0 and smaller thanL, L may be the CPM size of the PCM, Q₁ may be M₁/L, M₁ may be the sizeof the first parity part, Q₂ may be M₂/L, and M₂ may be the size of thesecond parity part.

In this case, it may be possible to perform the accumulation whilerepeatedly changing the rows of the sequence by the CPM size L (=360) ofthe PCM, as described above.

In this case, the first parity part λ_(K), λ_(K+1), . . . , λ_(K+M) ₁ ⁻¹may be generated by performing parity interleaving using the firstmemory and the second memory, as described in conjunction with Equation7.

In this case, the second parity part λ_(K+M) ₁ , λ_(K+M) ₁ ₊₁, . . . ,λ_(K+M) ₁ _(+M) ₂ ⁻¹ may be generated by performing parity interleavingusing the first memory and the second memory after generating the firstparity part λ_(K), λ_(K+1), . . . , λ_(K+M) ₁ ⁻¹ and then performing theaccumulation using the first parity part λ_(K), λ_(K+1), . . . , λ_(K+M)₁ ⁻¹ and the sequence, as described in conjunction with Equation 8.

FIG. 8 is an operation flowchart illustrating a bit interleaving methodaccording to an embodiment of the present invention.

Referring to FIG. 8, in the bit interleaving method according to thepresent embodiment, an LDPC codeword having a length of 16200 and a coderate of 4/15 is stored at step S810.

In this case, the LDPC codeword may be represented by (u₀, u₁, . . . ,u_(N) _(ldpc) ⁻¹) (where N_(ldpc) is 16200), and may be divided into 45bit groups each composed of 360 bits, as in Equation 9.

Furthermore, in the bit interleaving method according to the presentembodiment, an interleaved codeword is generated by interleaving theLDPC codeword on a bit group basis at step S820.

In this case, the size of the bit group may correspond to the parallelfactor of the LDPC codeword.

In this case, the interleaving may be performed using Equation 10 usingpermutation order.

In this case, the permutation order may correspond to the interleavingsequence represented by Equation 11.

In this case, the parallel factor may be 360, and each of the bit groupsmay include 360 bits.

In this case, the LDPC codeword may be divided into 45 bit groups, as inEquation 9.

Moreover, in the bit interleaving method according to the presentembodiment, the interleaved codeword is output to a modulator for16-symbol mapping at step 830.

In accordance with at least one embodiment of the present invention,there is provided an intra-BICM bit interleaver that can effectivelydistribute burst errors occurring in a broadcasting system channel.

In accordance with at least one embodiment of the present invention,there is provided a bit interleaver that is optimized for an LDPC coderhaving a length of 16200 and a code rate of 4/15 and a modulatorperforming 16-symbol mapping and, thus, can be applied tonext-generation broadcasting systems, such as ATSC 3.0.

Although the specific embodiments of the present invention have beendisclosed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible without departing from the scope and spirit of the invention asdisclosed in the accompanying claims.

What is claimed is:
 1. A bit group-unit interleaver, comprising: a firstmemory configured to store a low-density parity check (LDPC) codewordhaving a length of 16200 and a code rate of 4/15; a processor configuredto generate an interleaved codeword by interleaving the LDPC codeword ona bit group basis, the size of the bit group corresponding to a parallelfactor of the LDPC codeword; and a second memory configured to store theinterleaved codeword corresponding to a modulator for 16-symbol mapping,wherein the interleaving is performed using the following equation usingpermutation order:Y _(j) =X _(π(j)) 0≦j≦N _(group) where X_(π(j)) is a π(j)th bit group(X_(j) is a j-th bit group), Y_(j) is an interleaved j-th bit group,N_(group) is the number of bit groups obtained by dividing the LDPCcodeword into the bit groups, and π(j) is a permutation order for bitgroup-based interleaving, and wherein the permutation order correspondsto an interleaving sequence represented by the following interleavingsequence: {34 3 19 35 25 2 17 36 26 38 0 40 27 10 7 43 21 28 15 6 1 3718 30 32 33 29 22 12 13 5 23 44 14 4 31 20 39 42 11 9 16 41 8 24}, andwherein a modulated signal output from the modulator corresponds to atransmission signal, the transmission signal being transmitted to areception device.
 2. The bit group-unit interleaver of claim 1, whereinthe 16-symbol mapping is a Non-Uniform Constellation (NUC) symbolmapping which corresponds to 16 constellations.
 3. The bit group-unitinterleaver of claim 2, wherein the parallel factor is 360, and the bitgroup includes 360 bits.
 4. The bit group-unit interleaver of claim 3,wherein the LDPC codeword is represented by (u₀, u₁, . . . , u_(N)_(ldpc) ⁻¹) (where N_(ldpc) is 16200), and is divided into 45 bit groupseach including 360 bits, as in the following equation:X _(j) ={u _(k)|360×j≦k<360×(j+1), 0≦k<N _(ldpc)} for 0≦j<N _(group)where X_(j) is an j-th bit group, N_(ldpc) is 16200, and N_(group) is45.